1. Field of the Invention
The present invention relates to an apparatus and method for testing master logic units within a data processing apparatus.
2. Description of the Prior Art
A common technique for testing a logic unit within a data processing apparatus is to stimulate that logic unit""s inputs with test data and to capture the outputs via test accesses. These test accesses are seen as normal accesses by the logic unit (often referred to as the xe2x80x9cUnit Under Testxe2x80x9d (UUT)), the only difference being that the accesses are stimulated and controlled externally via a test interface driver, which is coupled to the data processing apparatus via a dedicated test access port.
This approach works well for UUTs that are designed to be recipients of processing requests rather than initiating such processing requests. Such logic units can be referred to as xe2x80x9cslavexe2x80x9d logic units, whereas logic units that are designed to initiate processing requests can be referred to as xe2x80x9cmasterxe2x80x9d logic units.
When testing master logic units using the above technique, the UUT needs to be reconfigured so that it can act as a recipient of processing requests generated by a test controller. This reconfiguration allows testing of the internal logic of the master logic unit to a certain extent, but requires special logic to be incorporated for test purposes. The special logic is used to drive the internal inputs (that in normal conditions would be provided by the slave that is communicating with the master), and to sample the outputs (that in normal conditions will be destined for the slave that is communicating with the master).
The overhead of this extra test logic is often justified by the intrinsic complexity and size of the master logic unit""s internal logic. However, there are a significant number of cases where the small size and complexity of the master logic unit does not justify the comparatively large test logic overhead.
Further, although this extra test logic allows a significant part of the master logic unit""s internal logic to be validated, the interface and the associated logic that enables the master logic unit to drive processing requests onto the system bus (ie the logic that enables the master logic unit to act as a xe2x80x9cmasterxe2x80x9d) remains untested.
An object of the present invention is to provide a technique which allows more effective testing of a master logic unit within a data processing apparatus.
Viewed from a first aspect, the present invention provides a data processing apparatus, comprising: one or more master logic units for accessing a bus in order to generate processing requests; a test controller for testing logic units of the data processing apparatus; an arbiter for receiving bus request signals from the test controller and the one or more master logic units, and for applying predetermined priority criteria to control access to the bus by the test controller and the master logic units, the predetermined priority criteria identifying the relative priority of each master logic unit and the test controller; in a normal test mode, the test controller having a higher priority than any of the master logic units to be tested; and in a master test mode, when master functionality of a first master logic unit is to be tested by the test controller, the arbiter being arranged to receive a priority access signal to cause the arbiter to assign the first master logic unit a higher priority than the test controller, in order to allow the first master logic unit to have access to the bus in order to generate a test processing request.
In accordance with the present invention, the data processing apparatus has one or more master logic units which may access a bus in order to generate processing requests, and a test controller for testing logic units of the data processing apparatus. Predetermined priority criteria are provided identifying the relative priority of each master logic unit and the test controller, and an arbiter is provided for applying the predetermined priority criteria in order to determine which of the one or more master logic units or the test controller should have access to the bus at any particular moment in time. Indeed, the test controller is a master logic unit itself, and the arbiter merely treats the test controller as one of the master logic units. Only one master logic unit can access the bus at any particular moment in time, and the arbiter ensures that, of all the units requesting access to the bus, the unit having the highest priority (whether it be the test controller or one of the master logic units) is granted access to the bus.
In a normal test mode, the test controller has a higher priority than any of the master logic units being tested, and hence the master logic units being tested cannot be granted access to the bus whilst the test controller is performing testing. Hence, in normal test mode, the master logic unit under test is unable to drive processing requests onto the bus, and so the interface functionality of the master logic unit cannot be tested. However, in accordance with the present invention, a master test mode is provided, in which when master functionality of a first master logic unit is to be tested by the test controller, the arbiter is arranged to receive a priority access signal to cause the arbiter to assign the first master logic unit a higher priority than the test controller. This allows the first master logic unit to have access to the bus in order to generate a test processing request, even though the test controller may still be requesting access to the bus. By this approach, the master logic unit being tested is allowed to fully exercise its master functionality by allowing that master logic unit to drive processing requests onto the bus in a controlled manner.
Hence, it can be seen that the technique of the present invention enables the interface logic of the master logic unit to be tested, this also inherently causing parts of the core logic of the master logic unit that interact with the interface logic to be tested. This enables the complexity and size of the actual test logic provided within the master logic unit to test the core logic to be reduced over that required by the previously discussed prior art technique.
In preferred embodiments, upon completion of the test processing request, the priority access signal is deactivated, so that subsequent access to the bus is controlled by the predetermined priority criteria. Clearly, the exact moment in time at which the priority access signal is deactivated will depend on the manner in which the arbiter grants access to the bus, and hence the priority access signal can be deactivated at any appropriate point following completion of the test processing request by the first master logic unit. Further, in alternative embodiments, as will be discussed later, the priority access signal can be continuously asserted throughout a sequence of test processing requests, and then deactivated once the entire sequence of test processing requests has been completed.
Preferably, upon completion of the test processing request, the test controller is arranged to access the results of the test processing request performed by the first master logic unit. Since upon completion of the test processing request, the priority access signal is typically deactivated, thereby causing the arbiter to once again control access to the bus in accordance with the predetermined priority criteria, this enables the test controller to read the appropriate registers or memory locations in order to retrieve the results of the test processing request, and thereby determine whether the master logic unit being tested has functioned correctly.
The priority access signal may itself be a bus request signal issued instead of, or in addition to, the first master logic unit""s normal bus request signal when the master logic unit is being tested in the master test mode. However, in preferred embodiments, the priority access signal comprises a priority enable signal arranged to cause the arbiter to assign the first master logic unit a higher priority than the test controller, such that the first master logic unit will be given access to the bus upon issuing its normal bus request signal.
Preferably, the master logic unit is arranged to assert its normal bus request signal to request access to the bus in order to enable the test processing request to be driven onto the bus, and the arbiter is arranged to grant the first master logic unit access to the system bus if the priority enable signal is asserted. Further, the master logic unit is preferably arranged to disassert its normal bus request signal upon completion of the test processing request, thereby allowing the test controller to be granted access to the bus.
There are clearly many ways in which the priority access signal may be issued in the master test mode. For example, the test controller may itself be arranged to issue the priority access signal. However, this is not the preferred option, since it requires the test controller to have specific knowledge of the master logic units of the data processing apparatus, thereby inhibiting the provision of a generic test controller. Hence, in preferred embodiments, the first master logic unit is arranged to issue the priority access signal to the arbiter in the master test mode. More specifically, in preferred embodiments, the first master logic unit contains a test register from which the priority access signal is asserted, and the priority access signal is asserted to the arbiter by the first master logic unit when the first master logic unit is to be tested in said master test mode.
Further, upon initiating a test of the first master logic unit in said master test mode, the test controller is preferably arranged to cause the priority access signal to be asserted via the test register of the first master logic unit. In preferred embodiments this is achieved by arranging the test controller to write a first logic value into the test register to cause the priority access signal to be asserted. For example, a logic xe2x80x981xe2x80x99 value may be written into the test register by the test controller, in order to cause the priority access signal to be asserted.
In such an embodiment, a second logic value is preferably written into the test register to cause the priority access signal to be disasserted. This may be done on completion of the test processing request, or, as mentioned earlier, may be done after a predetermined sequence of test processing requests have been completed. Since in preferred embodiments, the priority access signal is a priority enable signal which allows the first master logic unit to be granted access to the bus when it issues its normal bus request signal, then the test controller can be granted access to the bus when the normal bus request signal of the first master logic unit is disasserted, even if the priority enable signal remains asserted. This enables a sequence of tests to be performed whilst the priority enable signal remains high.
There are clearly a number of ways in which the second logic value can be written into the test register to cause the priority access signal to be disasserted. For example, the first master logic unit may be arranged to cause the second logic value to be stored in the test register upon completing the test processing request. However, in preferred embodiments, upon being granted access to the bus after completion of the test processing request by the first master logic unit, the test controller is arranged to write a second logic value into the test register of the first master logic unit to cause the priority access signal to be disasserted. This latter approach is preferable, because the test controller retains control for disasserting the priority access signal, and hence the flexibility for performing a plurality of test sequences before disasserting the priority access signal is retained.
It will be appreciated by those skilled in the art that the exact construction of the arbiter is a matter of design choice. However, in preferred embodiments, the arbiter comprises a priority encoder for receiving the priority access signal and any bus request signals from the test controller and the one or more master logic units; the arbiter being arranged to apply the predetermined priority criteria in the absence of said priority access signal in order to generate a signal identifying which of the test controller and master logic units requesting the bus has the highest priority; and the arbiter being arranged upon receipt of the priority access signal to assign the first master logic unit a higher priority than the test controller irrespective of the predetermined priority criteria and to generate a signal identifying the highest priority master logic unit requesting the bus.
Preferably, the arbiter further comprises grant generation logic for receiving the signal from the priority encoder, and for sending a bus grant signal to the test controller or one of the master logic units, as identified by the signal from the priority encoder.
In preferred embodiments, the first master logic unit comprises test logic for controlling testing of the first master logic unit in said normal test mode. In preferred embodiments, no further test logic is required within the first master logic unit to enable the first master logic unit to be tested in the master test mode.
Viewed from a second aspect, the present invention provides a method of testing a master logic unit within a data processing apparatus, the data processing apparatus comprising one or more master logic units arranged to access a bus in order to generate processing requests, a test controller for testing logic units of the data processing apparatus, and an arbiter for receiving bus request signals from the test controller and the one or more master logic units, and for applying predetermined priority criteria to control access to the bus by the test controller and the master logic units, the predetermined priority criteria identifying the relative priority of each master logic unit and the test controller, the method comprising the steps of:
(a) arranging the test controller to initiate a test of master functionality of the first master logic unit in a master test mode;
(b) issuing a priority access signal to the arbiter to cause the arbiter to assign the first master logic unit a higher priority than the test controller;
(c) granting the first master logic unit access to the system bus; and
(d) arranging the first master logic unit to generate a test processing request.
In preferred embodiments, the priority access signal comprises a priority enable signal arranged to cause the arbiter to assign the first master logic unit a higher priority than the test controller, and said step (c) comprises granting the first master logic unit access to the bus when the first master logic unit issues its normal bus request signal.
Preferably, the master logic unit is arranged to assert its normal bus request signal to request access to the bus in order to enable the test processing request to be driven onto the bus, and the first master logic unit is granted access to the system bus at said step (c) if the priority enable signal is asserted. Further, the master logic unit is preferably arranged to disassert its normal bus request signal upon completion of the test processing request, thereby allowing the test controller to be granted access to the bus.
In preferred embodiments, said step (b) comprises the step of the first master logic unit asserting the priority access signal to the arbiter when the first master logic unit is to be tested in said master test mode. Further, upon initiating a test of the first master logic unit in said master test mode at said step (a), the test controller is preferably arranged to cause the priority access signal to be asserted by the first master logic unit at said step (b).